Prior art products in the field of channel-based global routers are known which utilize global routing graphs for routing electric connection lines between circuit modules and pins during semiconductor chip development. Fixed area-based global routers have been employed for establishing electrical connection schemes between source and target pins in fixed die designs. In the case of area-based global routers, regular sized global routing grids are employed. The major difference between kinds of routers which are employed in the prior art is whether the size of the routing region is variable or not.
A recent approach to routing is to use blocks or cells from a library containing reusable designs. Routing with such blocks and cells is made complicated, because the blocks and cells have standard sizes which are conventionally routed according to a fixed area routing approach, while the variable sized channels may conventionally be routed by another kind of router approach. In lieu of actually performing full fixed area routing over the blocks and cells, preprocessing can be done for the over the block routing. However, the result of this is that the number of pins per net are increased. Further, an increased level of computing complexities is employed and additionally the effect of this two step approach is that the quality of the routing itself is diminished.
It is accordingly desirable to perform routing in a manner which limits the total number of pins in a particular circuit interconnection scheme. It is further desirable to provide a fundamental solution in the nature of a generic global routing approach effective for accomplishing routing in one single step which can handle both fixed-sized area and variable-sized channel routing in one process.